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ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
congxianchaoshengshujucaiji
- 在研究超声检测技术以及高频信号采集和处理技术发展趋势和PCI总线的特点基 础上，提出了一种基于PCI总线的超声数据采集卡的实现方案。在硬件方面，系统由模 数转换模块、数据缓冲模块、接口模块和逻辑控制模块等四个功能模块构成，着重研究 了接口芯片PCI9052的数据传输方式，采用原理图+VHDL的方法设计了板卡的内部控 制逻辑和数据缓冲模块，并进行了相关的时序仿真和逻辑验证。-Ultrasonic testing in research and high-frequency sign
Program3
- 用 vhdl 语言设计 8 位数码扫描显示电路，显示输出数据直接在程序中给出。增加 8 个 4 位锁存器作为输出显示数据缓冲器，由外部输入8个待显示的十六进制数。-Design with vhdl language display 8-bit digital scanning circuit, display output data are given directly in the program. Increased eight 4-bit latch display data buffer
MP3-coder
- In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read t
FIFO
- FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
VmodCAM_Ref_HD Demo_13
- This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup. The proj